Jean Bélanger

An Equivalent Circuit Method for Modelling and Simulation of Modular Multilevel Converter in Real-time HIL Test Bench

Publication date : Oct 2016
Paper File : MMC_TPD_v10_sub_TPWRD-00813-2015.R1.pdf



Share this document:

Author(s)

Authors: Wei Li, Jean Bélanger,

Abstract

In China, two modular multilevel converter (MMC) projects were recently commissioned, and other two are currently under construction. The real time hardware-in-the-loop (HIL) test bench played an important role in validating the manufacturer’s controllers. The full detail MMC model does not fit with the HIL test bench, which has to solve the circuit containing numerous switches and handle a large amount of inputs and outputs (I/Os) at a small time step for real time simulation. The main challenge is to find a method to model and simulate the MMC systems with sufficient detail, accuracy, and speed. This paper presents an equivalent circuit method for the HIL test bench. The circuit inside sub-module (SM) is represented by mathematical equations, implemented in CPU or field-programmable gate array (FPGA), and solved in parallel to achieve real time performance. This method based test bench is used in those MMC projects in China and connected to the manufacturer’s controllers for HIL tests. The model accuracy and simulation speed achieved by this method met the requirements of the HIL tests. In this paper, various scenarios are tested in an MMC HVDC study system. The results achieved by the proposed method have high agreement with those of a reference model in EMTP-RV.

An FPGA-based Real-time HIL Test Bench for Full-Bridge Modular Multilevel STATCOM Controller

Publication date : May 2015
Paper File : EPE2015_MMCstatcom_v5.pdf



Share this document:

Author(s)

Authors: Wei Li, Jean Bélanger,

Abstract

The modular multilevel converter (MMC) STATCOM removes the need for AC filter and transformer, has no DC bus fault hazard, and thus becomes a better option than a 2-level voltage source converter (VSC) STATCOM. An MMC can have hundreds of submodules (SM). The switches in the SM are controlled individually and the capacitor voltages have to be balanced. Therefore, the control and protection system is sophisticated and has to be validated for different scenarios preferably by hardware-in-the-Loop (HIL) tests. Modeling MMC in detail and simulating it in real time has two main challenges: solving the large circuit containing numerous switches and handling numerous inputs and outputs (IO) in very small time steps. This paper presents a real time test bench, which implements the detailed MMC valve models in field programmable gate array (FPGA) boards and enables connecting to external controllers through high speed protocols used by MMC manufacturers. It can simulate very large systems, e.g. multiple MMC STATCOM and high voltage direct current (HVDC) systems with up to 1000 SM per valve, at multiple sampling rates in real time: the MMC valve is simulated in FPGA with a time step of 250 ns and the rest of the power system is simulated in central processing unit (CPU) cores with a time step of tens of microseconds. The detailed MMC model in the test bench is able to accurately reproduce system behaviors in steady state, transients and faults, which facilitate HIL tests of actual MMC controller for all scenarios in a close-to-reality environment.

ANALYSIS AND HARDWARE-IN-THE-LOOP SIMULATION OF A POLE-TO-POLE DC FAULT IN MMC-BASED HVDC SYSTEMS

Publication date : Sep 2015
Paper File : COBEP_SPEC2015_MMC_v5.pdf



Share this document:

Author(s)

Authors: Weihua Wang, Jin Zhu, Wei Li, Jean Bélanger,

Abstract

This paper analyzes the possible range of the DC currents developed by a pole-to-pole DC fault in a Modular Multilevel Converter (MMC) -based high voltage direct current (HVDC) system, using half-bridge submodules (SM), when the actual control and protection (C&P) scheme for the system recently installed in China is applied. The results derived from differential equations are validated by hardware-in-the-loop (HIL) simulation with the complete C&P equipment. Unlike an AC fault at the grid side, which may be tested on a physical test bench or even on the actual system, a pole-to-pole DC fault is so severe that it can be only studied with a real-time digital simulator (RTS), if the dynamic response of the actual C&P system is involved.

Hybrid CPU-Core and FPGA based real-time implementation of a high frequency aircraft power system

Publication date : Nov 2015
Paper File : Not available yet

Share this document:

Author(s)

T. Ilamparithi, Ohm Prakash, Jean Bélanger, Auteurs : K.S. Amitkumar,

Abstract

The concept of a More Electric Aircraft (MEA) power system is becoming increasingly popular, mainly due to its higher efficiency as compared to the conventional aircraft power system. This paper proposes and implements a section of an MEA system in real-time. The real-time implementation methodology presented in this paper utilizes both CPU-cores and an FPGA processor, depending on the time step requirement for each part of the proposed system. Several real-time implementation results are presented to validate the proposed implementation methodology. Further, dynamic studies and contingency studies are also presented to ensure that various bus voltages of the proposed MEA system are within specified ranges as per relevant standards.

FPGA-based Real-Time Simulation of a PSIM Model: An Indirect Matrix Converter Case Study

Publication date : Nov 2015
Paper File : FPGA-based Real-Time Simulation of a PSIM Model_IECON2015.pdf



Share this document:

Author(s)

Tarek Ould Bachir, Sébastien Cense, Jean Bélanger, Handy Fortin-Blanchette, Asma MERDASSI,

Abstract

In this paper, an indirect matrix converter (IMC) which makes directly ac-ac power conversion, is modeled and simulated in real-time to demonstrate the capability of the new link between Opal-RT’s eHS (electric Hardware Solver) and the CAD tool PSIM. An automatic methodology for the real-time simulation of power converters from PSIM circuit designs to FPGA is presented and discussed. A time-step of 250 ns is achieved on an FPGA computing engine developing up to 25.6 GFLOPS of processing power. Real-time simulation results are compared against PSIM as an offline validation tool, showing close match between the FPGA-based simulation and the reference.

Validation of Modular Multilevel Converter Real-Time Simulator in DC Pole-Pole Fault Scenario

Publication date : Sep 2015
Paper File : MMC_cigre 2015.pdf



Share this document:

Author(s)

OPAL-RT; Wei Li, Jean Bélanger,

Abstract

Real time simulator becomes an important tool for modular multilevel converter (MMC) manufacturers to test and validate their control and protection systems in hardware-in-the-loop (HIL) setup. The simulation of large MMC converters with several hundreds of cells per valve is, however, very complex and time consuming due to the large number of states and switches requiring re-computing of the total system states at each change of switch status. This is a challenge for off-line simulation tools to achieve an acceptable processing time and even more challenging for real-time simulators, which must complete the full model calculation within a few microseconds. Consequently, commercial off-line power system simulation software and real-time simulator solvers must optimize and simplify, to a certain extent, the MMC system model to achieve acceptable simulation times. In some literature, it was believed that the aggregated capacitor MMC model would be accurate enough to simulate the system dynamics of the MMC terminals and their adjacent networks, if the valve voltage balancing controller is not tested. Although the real time simulator using detailed submodule MMC model implemented on FPGA has already been used in and contributed to the Nan’ao and Zhoushan multi-terminal MMC projects, China, there is still skepticism about simulation fidelity: simulation errors could be introduced due to the model simplifications. Recently a Chinese MMC manufacturer tested their controller with two commercial HIL real-time simulators. In the DC pole-pole fault scenario, discrepancies were found in the DC fault current evaluated by different simulators using different model simplifications required to achieve real-time for HIL controller and protection testing. Because the DC fault current is important for calculating protection settings, the authors performed an investigation to analyse the effect on model simplifications, which could affect the DC fault current seen by the controller and protection systems, and propose a method to determine the possible range of expected DC fault current curve without the knowledge of the detailed controller. The analysis presented is applicable for both off-line and real-time simulation tools.

Factory Acceptance Test of a Five-terminal MMC Control and Protection System using Hardware-in-the-loop Method

Publication date : Jul 2015
Paper File : Factory Acceptance Test of a Five-terminal MMC Control and Protection System using Hardware-in-the-loop Method.pdf



Share this document:

Author(s)

Yunlong Dong, Weihua Wang, Wei Li, OPAL-RT, NR Electric, Jie Tian, Jean Bélanger, Gang Li,

Abstract

Being the first five-terminal Modular Multilevel Converter (MMC)-based HVDC project in the world, the control and protection system must be validated under various operation modes as well as contingency at the factory acceptance test. This paper presents the configuration and performance of a hardware-in-the-loop (HIL) test platform that is based on a multi-rate real-time simulator using commercial-off-the-shelf architecture. The MMC sub-module model is implemented in field programmable gate array (FPGA) boards with a computation cycle of 500 ns, while the rest of the power system is simulated on the central processing unit (standard multi-core CPU) with a time-step of 30 μs. The State-space Nodal (SSN) interface is used to couple the models simulated on FPGA and on CPU. In addition, a communication protocol based on Giga-bit Ethernet is designed to connect the actual valve balancing controller with the real-time simulator. Results from the factory acceptance test are presented in this paper.

Development of Real Time Digital Simulator for Self-Commutated SVC to Suppress Voltage Flicker

Publication date : May 2014
Paper File : IPEC2014.pdf



Share this document:

Author(s)

Yutaka Terao, Yoshinori Tsuruma, Yasuhiro Shishida, TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL, Tomotsugu Ishizuka, Teruo Yoshino, Fumio Aoyama, Yutaka Kato NEAT CO., Jean Bélanger,

Abstract

This paper deals with real-time simulation of a self-commutated static var compensator (SVC) system for steel plants with electric arc furnaces (EAFs). A voltage flicker often occurs due to the unsteady current and changes in reactive power. Simulation of the flicker suppression system is quite complicated, and new simulation techniques should be developed. We constructed a main circuit and control system models of an SVC for real-time simulation with RT-LAB®. The real-time simulation results were compared with actual operational data of a steel plant system equipped with two furnaces. Finally, we showed that we successfully developed a real-time simulation system for SVC systems.

An Induction Machine and Power Electronic Test System on FPGA

Publication date : Aug 2014
Paper File : FPGA_Induction_Machine_Electrimacs2014_DufourCense.pdf



Share this document:

Author(s)

Sébastien Cense, Jean Bélanger, Christian Dufour,

Abstract

This paper presents an FPGA test system composed of an Induction Machine (IM), configurable as a Doubly-Fed Induction Machine (DFIM) or squirrel-cage induction machine, along with power electronic models suitable for virtual motor drive control development. The IM model is designed so that all parameters can be modified online. The power electronic part is customizable using a variable topology FPGA solver called Electric Hardware Solver (eHS). The system is designed for fast design iteration process by allowing circuit and parameter modification with a unique bitstream. The system allows control engineers to validate production controllers in real-time using a virtual IM.

Syndicate content